module cntrl_unit( cntrl_in, cntrl_D, cntrl_X, cntrl_M,
                   s_z, ExtMux, Jump, Branch );
 input[4:0] cntrl_in; //inst[15:11]

 output[3:0] cntrl_D; //(ALUop) Jr, ALUsrc1, ALUsrc2, wb_pc
 output[1:0] cntrl_X; //MemRead, MemWrite
 output[1:0] cntrl_M; //MemtoReg, RegDst
 output s_z, ExtMux, Jump, Branch;//used within Decoding stage

 wire Jr, ALUsrc1, ALUsrc2, wb_pc;
 wire MemRead, MemWrite;
 wire MemtoReg, RegDst;

 
 


endmodule
